Low-power high-performance arithmetic circuits and architectures
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/21003/00974550.pdf?arnumber=974550
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Dynamic differential self-timed logic families for robust and low-power security ICs;Integration;2007-04
2. Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders;Microelectronics International;2005-12
3. A New Static Differential CMOS Logic with Superior Low Power Performance;Analog Integrated Circuits and Signal Processing;2005-05
4. Efficient algorithms for multilevel power estimation of VLSI circuits;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2005-02
5. Low power high-speed multithreshold voltage CMOS bus architectures;Computers & Electrical Engineering;2004-06
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