Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA-Reference-Cited by-同舟云学术

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Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA

Published:2015-08 Issue: Volume: Page:
ISSN:
Container-title:2015 Euromicro Conference on Digital System Design
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Author:

Rodrigues Tiago,Vestias Mario

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7302133/7302233/07302252.pdf?arnumber=7302252

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hardware Multi-Threaded System for High-Performance JPEG Decoding;Journal of Signal Processing Systems;2023-12-26

2. An FPGA‐based JPEG preprocessing accelerator for image classification;The Journal of Engineering;2022-07-22

3. Framework for Dynamic Partial Configuration of Algorithms for Zynq-7000 SoC using JPEG as Case Study;2022 2nd International Conference on Digital Futures and Transformative Technologies (ICoDT2);2022-05-24

4. Accelerating Deep Learning Tasks with Optimized GPU-assisted Image Decoding;2020 IEEE 26th International Conference on Parallel and Distributed Systems (ICPADS);2020-12

5. FPGA-Based Reconfigurable Data Acquisition System for Industrial Sensors;IEEE Transactions on Industrial Informatics;2017-08

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