Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis-Reference-Cited by-同舟云学术

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Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis

Published:2024-06-24 Issue: Volume: Page:99-114
ISSN:
Container-title:2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)
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Author:

Yüksel İsmail Emir¹,Tuğrul Yahya Can¹,Bostancı F. Nisa¹,Oliveira Geraldo F.¹,Yağlıkçı A. Giray¹,Olgun Ataberk¹,Soysal Melina¹,Luo Haocong¹,Gómez-Luna Juan¹,Sadrosadati Mohammad¹,Mutlu Onur¹

Affiliation:

1. ETH Zürich

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10646626/10646630/10647021.pdf?arnumber=10647021

Reference239 articles.

1. Processing data where it makes sense: Enabling in-memory computation

2. A Modern Primer on Processing in Memory;Mutlu,2021

3. Memory scaling: A systems architecture perspective

4. Research Problems and Opportunities in Memory Systems;Mutlu,2014

5. The tail at scale

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1. Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis;2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2024-06-24

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