Reliability of logic circuits under multiple simultaneous faults-Reference-Cited by-同舟云学术

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Reliability of logic circuits under multiple simultaneous faults

Published:2008-08 Issue: Volume: Page:
ISSN:
Container-title:2008 51st Midwest Symposium on Circuits and Systems
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Author:

Franco Denis Teixeira,Vasconcelos Mai Correia,Naviner Lirida,Naviner Jean-Francois

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4603800/4616714/04616787.pdf?arnumber=4616787

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach;Journal of Electronic Testing;2024-05-28

2. A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

3. Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning;2023 IEEE 24th Latin American Test Symposium (LATS);2023-03-21

4. An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation;Journal of Electronic Testing;2022-04

5. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults;Journal of Electronic Testing;2020-08

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