Machine Learning based Interconnect Parasitic R, C, and Power Estimation Analysis for Adder Family Circuits-Reference-Cited by-同舟云学术

Machine Learning based Interconnect Parasitic R, C, and Power Estimation Analysis for Adder Family Circuits

Published:2022-11-10 Issue: Volume: Page:
ISSN:
Container-title:2022 Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)
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Author:

Parvathi M¹

Affiliation:

1. BVRIT HYDERABAD College of Engineering for Women,Department of Electronics and Communication Engineering,Hyderabad,Telangana,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9986507/9986494/09987344.pdf?arnumber=9987344

Reference22 articles.

1. ML-Based Comparative Analysis of Interconnect RC Estimation in Progressive Stacked Circuits;parvathi;In proceedings (eds) Evolutionary Computing and Mobile Sustainable Networks Lecture Notes on Data Engineering and Communications Technologies,2021

2. MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design

3. AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation

4. Pre-layout parasitic estimation in interconnects

5. PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

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1. Full Swing Logic Based Full Adder for Low Power Applications;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024

2. Regression Analysis Based Circuit Power Estimation Technique;2023 International Conference on Evolutionary Algorithms and Soft Computing Techniques (EASCT);2023-10-20