Total Performance of 32-nm-Node Ultralow-$k$/Cu Dual-Damascene Interconnects Featuring Short-TAT Silylated Porous Silica $(k = \hbox{2.1})$

Author:

Oda Noriaki,Chikaki Shinichi,Kubota Takeo,Nakao Shinichi,Tomioka Kazuhiro,Soda Eiichi,Nakamura Naofumi,Gawase Akifumi,Nogawa Jun,Kawashima Yoshitsugu,Hayashi Ryo,Suzuki Tatsu,Saito Shuichi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Hollow Airgap Technology for CMOS Maximum Interconnect Capacitance Reduction;2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT);2022-10-25

2. Mechanically Stable Ultra-Low-K Dielectric and Air-Gap Technology;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26

3. Ultralow-${k}$ Dielectric With Structured Pores for Interconnect Delay Reduction;IEEE Transactions on Electron Devices;2020-05

4. Ultralow- $k$ Dielectric With Nanotubes Assisted Vertically Aligned Cylindrical Pores;IEEE Electron Device Letters;2016-11

5. Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes;Microelectronic Engineering;2014-04

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