Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers-Reference-Cited by-同舟云学术

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Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers

Published:2001 Issue:11 Volume:36 Page:1745-1755
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wicht B.,Paul S.,Schmitt-Landsiedel D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/20772/00962297.pdf?arnumber=962297

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

2. Optimization of 1KByte 6T SRAM using block partitioning method and gated Vdd concept;AIP Conference Proceedings;2019

3. Design and evaluation of a high-accuracy current sensing circuit;IEEJ Transactions on Electrical and Electronic Engineering;2018-06-25

4. Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity;2015 IEEE International Symposium on Nanoelectronic and Information Systems;2015-12

5. Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ I CELL SRAM in FinFET with Improved Offset Tolerance;Circuits, Systems, and Signal Processing;2015-11-24

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