Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock
Author:
Funder
German Federal Ministry of Education and Research
German Research Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9682201/9682202/09682471.pdf?arnumber=9682471
Reference7 articles.
1. A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology
2. 64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology
3. Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications
4. A 112-GS/s 1-to-4 ADC front-end with more than 35-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS
5. 200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator
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1. A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process;IEICE Electronics Express;2024-08-10
2. A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process;IEICE ELECTRON EXPR;2024
3. Neuromorphic computing by means of recurrent spectrum slicing for next generation high baud rate transmission systems;2023 IEEE Photonics Society Summer Topicals Meeting Series (SUM);2023-07
4. Self-Coherent Receiver Based on a Recurrent Optical Spectrum Slicing Neuromorphic Accelerator;Journal of Lightwave Technology;2023
5. Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s;IEEE Journal of Solid-State Circuits;2022-09
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