High-Speed TLP and ESD Characterization of ICs-Reference-Cited by-同舟云学术

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High-Speed TLP and ESD Characterization of ICs

Published:2021-12-05 Issue: Volume: Page:
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Container-title:2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)
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Author:

Muhonen Kathleen,Grund Evan,Ashton Robert

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9682201/9682202/09682498.pdf?arnumber=9682498

Reference9 articles.

1. Transmission line pulsing techniques for circuit modeling of ESD phenomena;maloney;EOS/ESD Symp Proc,1985

2. For Electrostatic Discharge Sensistivty Testing - Transmission Line Puls (TLP) - Component Level;ANSI/ESD STM5 5 1,2017

3. ESD Parameter Extraction by TLP Measurement;fukuda;EOS/ESD Symp Proc,2009

4. Using VFTLP Data to Design for CDM Robustness;chu;EOS/ESD Symp Proc,2009

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Balanced method of Clamp Distribution and Placement in an IO ring;2023 IEEE Women in Technology Conference (WINTECHCON);2023-09-21

2. MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application;Micromachines;2023-03-10

3. ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation;2022 IEEE International Conference on Consumer Electronics - Taiwan;2022-07-06

4. HV 65V nLDMOSs Engineering of ESD Enhancement by the Drain Side with Parasitic SCR Modulations;2022 8th International Conference on Applied System Innovation (ICASI);2022-04-22

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