MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application
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Published:2023-03-10
Issue:3
Volume:14
Page:632
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
Chen Ruibo1, Wei Hao1ORCID, Liu Hongxia1ORCID, Hou Fei2, Xiang Qi1, Du Feibo2, Yan Cong1, Gao Tianzhi1ORCID, Liu Zhiwei2
Affiliation:
1. Key Laboratory for Wide-Band Gap Semiconductor Materials and Devices of Education, School of Microelectronics, Xidian University, Xi’an 710071, China 2. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610056, China
Abstract
In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.
Funder
National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference27 articles.
1. Duvvury, C. (2008, January 15–17). ESD qualification changes for 45 nm and beyond IEEE Int. Proceedings of the 2018 Electron Devices Meeting, San Francisco, CA, USA. 2. An enhanced gate-grounded NMOSFET for robust ESD applications;Du;IEEE Electron Device Lett.,2019 3. Li, J., and Halbach, R. (2006, January 3–7). Analysis of failure mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65 nm Bulk CMOS technology int. Proceedings of the 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore. 4. Kim, C.S., Park, H.B., Kim, B.G., Kang, D.G., Lee, M.G., Lee, S.W., Jeon, C.H., Kim, W.G., Yoo, Y.J., and Yoon, H.S. (2000, January 26–28). A novel NMOS transistor for high performance ESD protection devices in 0.18/spl mu/m CMOS technology utilizing salicide process. Proceedings of the Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No. 00TH8476), Anaheim, CA, USA. 5. Overview of on-chip electronstatic discharge protection design with SCR-base devices in CMOS integrated circuits;Ker;IEEE Trans. Device Mater. Rel.,2005
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