Design and Characterization of High-Voltage NMOS Structures in a 0.5 $\mu{\rm m}$ Standard CMOS Process-Reference-Cited by-同舟云学术

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Design and Characterization of High-Voltage NMOS Structures in a 0.5 $\mu{\rm m}$ Standard CMOS Process

Published:2013-08 Issue:8 Volume:13 Page:2906-2913
ISSN:1530-437X
Container-title:IEEE Sensors Journal
language:
Short-container-title:IEEE Sensors J.

Author:

Lee Tsung-Hsueh,Abshire Pamela A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/7361/6553369/06517251.pdf?arnumber=6517251

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Silicon carbide planar junctionless transistor for low-medium voltage power electronics;Journal of Physics Communications;2021-02-01

2. Design of Drain-Extended MOS Devices Using RESURF Techniques for High Switching Performance and Avalanche Reliability;IEEE Access;2021

3. Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation;IEEE Transactions on Electron Devices;2018-11

4. Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture;IEEE Journal of the Electron Devices Society;2018

5. Non-logic MOSFETs in Logic CMOS Processes;Non-logic Devices in Logic Processes;2017

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