A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS
Author:
Affiliation:
1. School of Microelectronics, Southern University of Science and Technology
2. School of Microelectronics, Xi'an Jiaotong University
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9687621/9687623/09687686.pdf?arnumber=9687686
Reference11 articles.
1. A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS
2. A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS
3. 100 Gb/s Differential Linear TIAs With Less Than 10 pA/ $\sqrt {\mathrm {Hz}}$ in 130-nm SiGe:C BiCMOS
4. A 40 Gb/s Monolithically Integrated Linear Photonic Receiver in a $0.25~\mu {\rm m}$ BiCMOS SiGe:C Technology
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