The Impact of Inner Pickup on ESD Robustness of Multi-Finger NMOS in Nanoscale CMOS Technology
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4017118/4017119/04017238.pdf?arnumber=4017238
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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2. Improving Safe-Operating-Area of a 5-V n-Channel Large Array MOSFET in a 0.15- $\mu$ m BCD Process;IEEE Transactions on Electron Devices;2018-07
3. Compact distributed multi-finger MOSFET model for circuit-level ESD simulation;Microelectronics Reliability;2016-08
4. Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes;IETE Journal of Research;2016-04-07
5. Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process;IEICE Transactions on Electronics;2016
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