Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier

Author:

Chin Koken,San Hao,Kitajima Atsushi,Arai Yoshiaki,Yamashita Jun,Ito Hisashi

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An approach for designing leakage compensated voltage reference circuit;International Journal of Electronics;2024-02-06

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3. 21.2 A $\boldsymbol{22\mu \mathrm{W}}$ Peak Power Multimodal Electrochemical Sensor Interface IC for Bioreactor Monitoring;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

4. Input bias current reduction technique for operational amplifier in a standard CMOS technology;Electronics and Communications in Japan;2020-05-16

5. Input Bias Current Reduction Technique for Operational Amplifier in a Standard CMOS Technology;IEEJ Transactions on Electronics, Information and Systems;2020-01-01

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