Input Bias Current Reduction Technique for Operational Amplifier in a Standard CMOS Technology
Author:
Affiliation:
1. New Japan Radio Co., Ltd
2. Tokyo City University
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)
Subject
Electrical and Electronic Engineering
Link
https://www.jstage.jst.go.jp/article/ieejeiss/140/1/140_9/_pdf
Reference4 articles.
1. (1) K. J. Carrol : “Integrated Electrostatic Discharge (ESD) Protection Circuitry For Signal Electrode”, U.S. Patent 11/948, 443 (2007)
2. (2) B. L. Anderson and R. L. Anderson : Fundamentals of Semiconductor Devices, McGraw-Hill Education, p. 816 (2005)
3. (3) K. Chin, A. Kitajima, Y. Arai, J. Yamashita, H. Ito, and H. San : “Leakage Current Compensation Technique of ESD Protection Circuit for CMOS Operational Amplifier”, The 2016 International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2016), pp. 518-521 (2016)
4. (4) JEITA : “Environmental and endurance test methods for semiconductor devices”, EIAJ ED-4701/300 (2001)
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