Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8910142/8923116/08923263.pdf?arnumber=8923263
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
2. Integration of Simulated Quantum Annealing in Parallel Tempering and Population Annealing for Heterogeneous-Profile QUBO Exploration;IEEE Access;2023
3. Input Data Format for Sparse Matrix in Quantum Annealing Emulator;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2023
4. FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model;2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2022-12
5. A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
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