FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model
Author:
Affiliation:
1. Tohoku University,Graduate School of Information Sciences,Sendai,Miyagi,Japan,980-8579
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10008388/10008225/10008441.pdf?arnumber=10008441
Reference25 articles.
1. A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing
2. An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method
3. Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL
4. Performance potential for simulating spin models on GPU
5. Systematic and deterministic graph minor embedding for Cartesian products of graphs
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