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Optimal Reconfiguration of High-Performance VLSI Subarrays with Network Flow

  • Published:2016-12-01 Issue:12 Volume:27 Page:3575-3587
  • ISSN:1045-9219
  • Container-title:IEEE Transactions on Parallel and Distributed Systems
  • language:
  • Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Qian JunyanORCID,Zhou Zhide,Gu Tianlong,Zhao Lingzhong,Chang Liang

Funder

National Natural Science Foundation of China

High Level Innovation Team of Guangxi Colleges and Universities

Outstanding Scholars Fund

Guangxi Natural Science Foundation of China

Guilin University of Electronic Technology

Guangxi Key Laboratory of Trusted Software Focus Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

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1. An Efficient Bottleneck Planes Exclusion Method for Reconfiguring 3D VLSI Arrays;IEEE Transactions on Parallel and Distributed Systems;2024-02

2. Efficient Three-Dimensional Processor Array Reconfiguration Algorithms Based on Bucket Effect;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023

3. Fault-Tolerant Deep Learning Processors;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023

4. Reconfiguration algorithms for synchronous communication on switch based degradable arrays;Parallel Computing;2022-07

5. Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25
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