SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP-Reference-Cited by-同舟云学术

SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

Published:2023 Issue: Volume: Page:1-11
ISSN:1077-260X
Container-title:IEEE Journal of Selected Topics in Quantum Electronics
language:
Short-container-title:IEEE J. Select. Topics Quantum Electron.

Author:

Ha Won-Yong¹,Park Eunsung²,Eom Doyoon²,Park Hyo-Sung²,Gramuglia Francesco³,Keshavarzian Pouyan⁴,Kizilkan Ekin⁴,Bruschini Claudio⁴,Chong Daniel³,Tan Shyue Seng³,Tng Michelle³,Quek Elgin³,Charbon Edoardo⁴,Choi Woo-Young⁵,Lee Myung-Jae²

Affiliation:

1. Post-Silicon Semiconductor Institute, Korea Institute of Science and Technology (KIST), and the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea

2. Post-Silicon Semiconductor Institute, Korea Institute of Science and Technology (KIST), Seoul, South Korea

3. GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D Street 2, Singapore

4. Institute of Electrical and Microengineering, École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel, Switzerland

5. Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea

Funder

Institutional Program

Korea Institute of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Atomic and Molecular Physics, and Optics

Link

http://xplorestaging.ieee.org/ielx7/2944/4481213/10214077.pdf?arnumber=10214077

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