The Impact of BTI Variations on Timing in Digital Logic Circuits-Reference-Cited by-同舟云学术

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The Impact of BTI Variations on Timing in Digital Logic Circuits

Published:2013-03 Issue:1 Volume:13 Page:277-286
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Fang Jianxin,Sapatnekar Sachin S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/7298/6472755/06407977.pdf?arnumber=6407977

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Long-Term Aging Impacts on Spatial On-Chip Power Density and Temperature;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

3. Development and Challenges of Reliability Modeling From Transistors to Circuits;IEEE Journal of the Electron Devices Society;2023

4. A Novel Low-Power NMOS Schmitt Trigger Circuit Using Voltage Bootstrapping and Transistor Stacking;Advances in Cognitive Science and Communications;2023

5. Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

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