Development and Challenges of Reliability Modeling From Transistors to Circuits-Reference-Cited by-同舟云学术

Development and Challenges of Reliability Modeling From Transistors to Circuits

Published:2023 Issue: Volume:11 Page:179-189
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Yang Xinhuan¹^ORCID,Sang Qianqian¹^ORCID,Wang Chuanzheng²,Yu Mingyan²,Zhao Yuanfu²

Affiliation:

1. School of Electronic Information, Hangzhou Dianzi University, Hangzhou, China

2. Faculty of Electronic Information, Hangzhou Dianzi University, Hangzhou, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Link

http://xplorestaging.ieee.org/ielx7/6245494/10049274/10058971.pdf?arnumber=10058971

Reference63 articles.

1. Extraction of Interface Trap Density Through Synchronized Optical Charge Pumping in Gate-All-Around MOSFETs

2. Learning-based BTI stress estimation and mitigation in multi-core processor systems

3. Experimental Monitoring of Aging in CMOS RF Linear Power Amplifiers: Correlation Between Device and Circuit Degradation

4. A unified physical BTI compact model in variability-aware DTCO Flow: Device characterization and circuit evaluation on reliability of scaling technology nodes;zhao;Proc Symp VLSI Technol,2021

5. Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress

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