Unexpected Latch-Up Through CMOS Triple-Well Structures-Reference-Cited by-同舟云学术

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Unexpected Latch-Up Through CMOS Triple-Well Structures

Published:2015-09 Issue:3 Volume:15 Page:272-279
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Stockinger Michael,Secareanu Radu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/7298/7234980/07185348.pdf?arnumber=7185348

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

2. Dynamic electrostatic-discharge path investigation relied on different impact energies in metal–oxide–semiconductor circuits;Chinese Physics B;2023-04-01

3. Gate Voltages Impacting on Latch-up Measurements;2022 IEEE International Conference on Consumer Electronics - Taiwan;2022-07-06

4. A PMOS Switch Body and Gate Control Circuit for USB3.2 Compliant Receiver;2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS);2020-08

5. Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs;IEICE Transactions on Electronics;2017

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