Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs-Reference-Cited by-同舟云学术

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs

Published:2017 Issue:5 Volume:E100.C Page:446-452
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

CHEN Shen-Li¹,HUANG Yu-Ting²,WU Yi-Cih¹

Affiliation:

1. Dept. of Electronic Engineering, National United University

2. IP technology service group, Powerchip Technology Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E100.C/5/E100.C_446/_pdf

Reference36 articles.

1. [1] C.-Y. Wu, M.-D. Ker, C.-Y. Lee, and J. Ko, “A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI,” IEEE Journal of Solid-State Circuits, vol.27, no.3, pp.274-280, 1992.

2. [2] J.C. Smith and G. Boselli, “A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies,” Electrical Overstress/Electrostatic Discharge Symposium, Las Vegas, USA, pp.1-9, Sept. 2003.

3. [3] J. Li, R. Gauthier, and E. Rosenbaum, “A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection,” Electrical Overstress/Electrostatic Discharge Symposium, Grapevine, USA, pp.1-7, Sept. 2004.

4. [4] J. Li, R. Gauthier, S. Mitra, C. Putnam, K. Chatty, R. Halbach, and C. Seguin, “Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection,” Electrical Overstress/Electrostatic Discharge Symposium, Tucson, Arizona, USA, pp.179-185, Sept. 2006.

5. [5] Q. Cui, Y. Han, J.J. Liou, S. Dong, R. Si, and C. Peng, “A Method to Model MOSFET's Second Breakdown Action for Circuit-Level ESD Simulation,” In International Symposium on High Density packaging and Microsystem Integration, Shanghai, China, pp.1-4, June 2007.