A comparative study on adders
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8292786/8299705/08300155.pdf?arnumber=8300155
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Way to Optimize Delay of Carry-Skip Adders by Using Blocks of Variable Sizes;Highlights in Science, Engineering and Technology;2023-11-28
2. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
3. Optimization of ALU with gated clock and its internal modules in RVIM64 processor;Journal of Physics: Conference Series;2023-10-01
4. Design and Implementation of an Optimized High-Speed Vedic-Based Squarer Circuit Using Reversible Logic Gates;Lecture Notes in Electrical Engineering;2023-09-03
5. Analysis of Area Efficient Parallel FIR Filters using FPGA;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
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