Author:
Bo Liu ,Frenzel J.F.,Wells R.B.
Cited by
4 articles.
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1. MVL Random Access Memory;Beyond Binary Memory Circuits;2022
2. A predischarged bitline 1T-1C DRAM readout scheme;Microelectronics Journal;2019-01
3. Memristor-Based Hardware Accelerator for Image Compression;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-12
4. Reading DRAM cells using two properly designed cascaded inverters;e & i Elektrotechnik und Informationstechnik;2014-03