Reading DRAM cells using two properly designed cascaded inverters-Reference-Cited by-同舟云学术

Reading DRAM cells using two properly designed cascaded inverters

Published:2014-03 Issue:2 Volume:131 Page:41-52
ISSN:0932-383X
Container-title:e & i Elektrotechnik und Informationstechnik
language:en
Short-container-title:Elektrotech. Inftech.

Author:

Sharroush Sherif M.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/s00502-014-0198-9.pdf

Reference14 articles.

1. Wood, J., Wood, R. G. (1965): The use of insulated-gate field-effect transistors in digital storage systems. In: ISSCC digest of technical papers, February 1965 (pp. 82–83).

2. Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC), February of each year.

3. Regitz, W. M., Karp, J. A. (1970): A three-transistor cell, 1024-bit, 500 ns MOS RAM. In ISSCC digest of technical papers, February 1970 (pp. 36–39).

4. Digest of the IEEE international electron devices meeting (IEDM), December of each year.

5. Dennard, R. H., et al. (1967): Field-effect transistor memory, U.S. Patent no. 3387286, 14 July 1967.

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