Metal Gate Recessed Access Device (RAD) for DRAM Scaling-Reference-Cited by-同舟云学术

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Metal Gate Recessed Access Device (RAD) for DRAM Scaling

Published:2007-04 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE Workshop on Microelectronics and Electron Devices
language:
Short-container-title:

Author:

Ramaswamy Nirmal,Ananthan Venkat,Hwang David,Iyer Ravi,Mouli Chandra,Mcteer Allen,Tang Sanh,Parekh Kunal,Owens Tim,Kim Young Pil,Palaniappan Nanda,Li Jian,Groothuis Steve,Haller Gordon,Wang Shixin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4218968/4218969/04218999.pdf?arnumber=4218999

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Roles of Residual Stress in Dynamic Refresh Failure of a Buried-Recessed-Channel-Array Transistor (B-CAT) in DRAM;IEEE Electron Device Letters;2016-07

2. Atomic layer deposition of TaN and Ta3N5 using pentakis(dimethylamino)tantalum and either ammonia or monomethylhydrazine;Journal of Crystal Growth;2011-09

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