Author:
Al-Ars Z.,Hamdioui S.,Mueller G.,van de Goor A.J.
Cited by
4 articles.
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1. Models in Memory Testing;Models in Hardware Testing;2009-10-27
2. Automating defects simulation and fault modeling for SRAMs;2008 IEEE International High Level Design Validation and Test Workshop;2008-11
3. Test Set Development for Cache Memory in Modern Microprocessors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2008-06
4. Trends in tests and failure mechanisms in deep sub-micron technologies;International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.;2006