Design of high performance and low power multiplier using modified booth encoder-Reference-Cited by-同舟云学术

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Design of high performance and low power multiplier using modified booth encoder

Published:2016-03 Issue: Volume: Page:
ISSN:
Container-title:2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)
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Author:

Prathiba R.,Sandhya P.,Varun R.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7731602/7754737/07754795.pdf?arnumber=7754795

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low Power Multiplier Using Approximate Adder for Error Tolerant Applications;IETE Journal of Research;2024-09-11

2. Low power multiplier based long short-term memory hardware architecture for smart grid energy management;International Journal of System Assurance Engineering and Management;2022-04-15

3. Reference signal less Fourier analysis based motion artifact removal algorithm for wearable photoplethysmography devices to estimate heart rate during physical exercises;Computers in Biology and Medicine;2022-02

4. Performance Improvement of Radix-4 Booth Multiplier on Negative Partial Products;2021 6th International Conference on Integrated Circuits and Microsystems (ICICM);2021-10-22

5. Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach;Circuits, Systems, and Signal Processing;2021-03-18

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