The Study on the Optimization and Electrical Behavior of NEDMOS Transistors for High-Voltage Power Applications
Author:
Affiliation:
1. Shanghai Huali Microelectronics Corporation, No. 568 Gaosi Road,Shanghai,People’s Republic of China,201620
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10219185/10219154/10219388.pdf?arnumber=10219388
Reference5 articles.
1. Silicon-on-Insulator Lateral DMOS With Potential Modulation Plates and Multiple Deep-Oxide Trenches
2. Hot-Carrier-Induced Reliability Concerns for Lateral DMOS Transistors with Split-STI Structures
3. Parasitic NPN and PNP Latch-Up Within a Single DMOS for High Voltage Reliability
4. Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures
5. Abnormal On-Current Degradation Under Non-Conductive Stress in Contact Field Plate Lateral Double-Diffused Metal-Oxide- Semiconductor Transistor With 0.13-μm Bipolar-CMOS-DMOS Technology
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