Performance Analysis of 6T and 11T SRAM Cell Topologies at 45nm Era
Author:
Affiliation:
1. GLA University,Electronics and Communication Department,Mathura,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9725432/9725433/09726111.pdf?arnumber=9726111
Reference20 articles.
1. LECTOR: a technique for leakage reduction in CMOS circuits
2. A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability
3. Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node
4. Leakage Minimization Technique for Nanoscale CMOS VLSI
5. Normal and Abnormal Spillage Suppression Methodologies for the SRAM Sense Amplifiers
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2. A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm And 45nm CMOS Technology;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23
3. Design and Parametric Analysis of 6T SRAM Using 180nm and 45nm Technology;2023 International Conference on Network, Multimedia and Information Technology (NMITCON);2023-09-01
4. Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
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