Design and Analysis of Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization

Author:

Nagarajan P.1,Thandapani Kavitha2,Ashokkumar N.3,Pappa C. Kanmani2

Affiliation:

1. SRM Institute of Science and Technology,Department of Electronics and communication Engineering,Chennai,Tamilnadu,India

2. Vel Tech Rangarajan Dr Sagunthala R&D Institute of Science and Technology,Chennai,TamilNadu,India

3. Sree Vidyanikethan Engineering College,Tirupati,AndraPradesh

Publisher

IEEE

Reference15 articles.

1. Design of a CMOS PFD-CP module for a PLL

2. Fast Charge Pump Circuit for PLL Using 50 nm CMOS Technology;singh;International Journal of Advanced Research in Computer and Communication Engineering,2013

3. Study of Recent Charge Pump Circuits in Phase Locked Loop

4. Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology;anshul;International Journal of Computer Applications,2015

5. A Charge Pump Current Mismatch Compensation Design for Sub-Sampling PLL

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A high voltage charge pump circuit for H bridge high side drive;Proceedings of the 2023 7th International Conference on Electronic Information Technology and Computer Engineering;2023-10-20

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