High-Performance Digital Signal Processing Circuit Design and Analysis for Wireless Communication Systems-Reference-Cited by-同舟云学术

High-Performance Digital Signal Processing Circuit Design and Analysis for Wireless Communication Systems

Published:2023-09-20 Issue: Volume: Page:
ISSN:
Container-title:2023 4th International Conference on Smart Electronics and Communication (ICOSEC)
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Author:

Kanika ¹,Shankar R.²,Eswaramoorthi R.³,Jeya Sheela J. Joselin⁴,Suri Ashish⁵,Vellachi N.⁶

Affiliation:

1. SRM Institute of Science and Technology,Department of Computer Science and Engineering,Ghaziabad,Uttar Pradesh,India,201204

2. Kongunadu College of Engineering and Technology,Department of Electrical and Electronic Engineering,Thottiam,India,621215

3. K S R College of Engineering (Autonomous),Department of Electronics and Communication Engineering,Namakal,Tamil Nadu,India,637215

4. Saveetha School of Engineering,Department of Electronics and Communication Engineering,Chennai,Tamil Nadu,India,602105

5. School of Electronics and Communication Engineering, Shri Mata Vaishno Devi University,Katra,Jammu and Kashmir,India,182320

6. PSNA College of Engineering and Technology (Autonomous),Department of Physics,Dindigul,Tamil Nadu,India,624622

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10275782/10275807/10276043.pdf?arnumber=10276043

Reference17 articles.

1. Design of a 1GHz Digital PLL Using 0. 18 ?m CMOS Technology;janardhan;IEEE Proc Of the Third International Conference on Information Technology,2006

2. A 10 GHz Phase-Locked Loop with a Compact Low-Pass Filter in 0. 18 ?m CMOS Technology;li;IEEE Microwave and Wireless Components Letters,2009

3. Oscillator phase noise: a tutorial

4. Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops

5. A fully integrated CMOS voltage regulator for supply-noise-insensitive charge pump PLL design