Novel Approach To Resolve Strip Camber At Assembly Process Of Semiconductor Packaging
Author:
Affiliation:
1. ASE Electronics (M) Sdn Bhd.,Quality Assurance Department,Penang,Malaysia
2. ASE Electronics (M) Sdn Bhd.,FOL Engineering Department,Penang,Malaysia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10248978/10248979/10249088.pdf?arnumber=10249088
Reference6 articles.
1. Strip warpage analysis of a flip chip package considering the mold compound processing parameters
2. Method for Mitigating the Warpage of Ultra-Thin FC-CSPs by Controlling of EMC Properties
3. BGA strip warpage induced by assembly process and the practical prediction methodology
4. Study on the Strip Warpage Issues Encountered in the Flip-Chip Process
5. Process and Packaging Innovations for Moore’s Law Continuation and beyond;chau;Tech Dig - Int Electron Devices Meet IEDM,2019
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