Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9337288/9337294/09337348.pdf?arnumber=9337348
Reference9 articles.
1. An RF module including a signal generator for a flexible and accurate APAA
2. Frequency and Phase Difference Control Using Fractional-$N$ PLL Synthesizers by Composition of Control Data
3. A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
4. A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector
5. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$
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