Author:
Chang Wei-Sung,Huang Po-Chun,Lee Tai-Cheng
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
49 articles.
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1. Design of Low Phase Noise PLL with Improved Locking Time;Lecture Notes in Electrical Engineering;2024
2. A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer;Synthesis Lectures on Engineering, Science, and Technology;2024
3. A 10 GHz Sub-Sampling PLL Chirp Synthesizer Using a Charge-Integrating DAC;Synthesis Lectures on Engineering, Science, and Technology;2024
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5. A 12~14.6GHz Fractional-N Sub-Sampling PLL for Wavelength Modulation Spectroscopy of CSMCs;2023 16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies (UCMMT);2023-08-31