Investigation on CMOS on-Chip Inductors Using Various Patterned Ground/Floating Shield Techniques-Reference-Cited by-同舟云学术

Investigation on CMOS on-Chip Inductors Using Various Patterned Ground/Floating Shield Techniques

Published:2021-12-10 Issue: Volume: Page:
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Container-title:2021 International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB)
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Author:

Wu Jhen-Nong¹,Chang Yan-Ming¹,Shen Zih-Yao¹,Chen Hsiao-Chin¹

Affiliation:

1. National Taiwan University of Science and Technology,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9686355/9686372/09686404.pdf?arnumber=9686404

Reference5 articles.

1. A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM

2. Research on the design techniques of Hilbert frad pattern ground shield;song;2017 International Applied Computational Electromagnetics Society Symposium (ACES),0

3. Development of scalable models for patterned-ground-shield inductors in SiGe BiCMOS technology

4. Shielded Passive Devices for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits

5. On-chip spiral inductors with patterned ground shields for Si-based RF ICs

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3. Fully Integrated Multi-layer Stacked Structure of Integrated Inductor with Patterned Ground Shield;2022 18th Biennial Baltic Electronics Conference (BEC);2022-10-04