Cost-Effective Co-Optimization of RF Process Technology Targeting Performances/Power/Area Enhancements for RF and mmWave Applications
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Published:2024-06-27
Issue:13
Volume:13
Page:2513
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Kim Sutae12, Lee Hyungjin2, Jeong Yongchae1
Affiliation:
1. Division of Electronic Engineering, Jeonbuk National University, Jeonju-si 54896, Jeollabuk-do, Republic of Korea 2. Samsung Electronics Co., Ltd., Samsungjeonja-ro, Hwaseong-si 18448, Gyeonggi-do, Republic of Korea
Abstract
In this paper, we propose a cost-effective way to tune RF process technology to achieve well-optimized RF and mmWave performances/power/area by tweaking back-end-of-line (BEOL) configurations. This paper suggests that the most favorable altitude is that of an ultra-thick-metal (UTM) layer from the silicon substrate, and the effort also focuses on the calibration of the via height/pitch underneath the UTM to satisfy the least ohmic loss in the interface between the active and passive device components. We implemented a process optimization in a 28 nm fully depleted silicon-on-insulator (FD-SOI) process technology, and the results show performance enhancements on the inductor, achieving a 14.8% quality factor improvement and a 13.1% self-resonance frequency improvement. This paper also showcases how the process optimization boosts 29 GHz LNA performances, with a 31.8% gain in boosting and a 9.1% reduction in noise-figure.
Reference10 articles.
1. Lee, H.J., Callender, S., Rami, S., Shin, W., Yu, Q., and Marulanda, J.M. (2020, January 22–25). Intel 22 nm Low-Power FinFET (22FFL) Process Technology for 5G and Beyond. Proceedings of the IEEE Custom Integrated Circuits Conference, Boston, MA, USA. 2. Ong, S.N., Lehmann, S., Chow, W.H., Zhang, C., Schippel, C., Chan, L.H., Andee, Y., Hauschildt, M., Tan, K.K., and Watts, J. (2018, January 10–12). A 22nm FDSOI Technology Optimized for RF/mmWave Applications. Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, USA. 3. Yu, Q., Garrett, J., Waldemer, J., Ma, Y., Ravikumar, S., Liu, G., and Rami, S. (2021, January 6–11). A mmWave Switch Using Novel Back-End-Of-Line (BEOL) in 22 nm FinFET Technology. Proceedings of the IEEE MTT-S International Microwave Symposium Digest, Atlanta, GA, USA. 4. Yu, Q., Kim, G.S., Garrett, J., Thomson, D., Dogiamis, G., Monroe, N., Han, R., Ma, Y., Waldemer, J., and Nam, Y.S. (2022, January 19–24). Low-Loss On-Chip Passive Circuits Using C4 Layer for RF, mmWave and sub-THz Applications. Proceedings of the IEEE MTT-S International Microwave Symposium Digest, Denver, CO, USA. 5. Dubuc, D., Tournier, E., Telliez, I., Parra, T., Boulanger, C., and Graffeuil, J. (2002, January 2–7). High quality factor and high self-resonant frequency monolithic inductor for millimeter-wave Si-based IC’s. Proceedings of the IEEE International Microwave Symposium Digest, Seattle, WA, USA.
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