Thread-level speculation on off-the-shelf hardware transactional memory-Reference-Cited by-同舟云学术

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Thread-level speculation on off-the-shelf hardware transactional memory

Published:2014-10 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Symposium on Workload Characterization (IISWC)
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Author:

Odaira Rei,Nakaike Takuya

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6966889/6983029/06983060.pdf?arnumber=6983060

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Evaluation on Parallel Speculation-Based Construction of a Binary Search Tree;International Journal of Networked and Distributed Computing;2023-11-08

2. Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

3. Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory;2022 21st International Symposium on Parallel and Distributed Computing (ISPDC);2022-07

4. Speculative Barriers With Transactional Memory;IEEE Transactions on Computers;2022-01-01

5. Loopapalooza: Investigating Limits of Loop-Level Parallelism with a Compiler-Driven Approach;2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2021-03

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