Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits-Reference-Cited by-同舟云学术

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Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

Published:1998-12 Issue:4 Volume:6 Page:538-545
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Pant P.,De V.K.,Chatterjee A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/15863/00736125.pdf?arnumber=736125

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Subthreshold Transistors;Advanced Ultra Low‐Power Semiconductor Devices;2023-10-27

2. Method of Generating Unique Elementary Circuit Topologies Méthode de génération de topologies de circuits élémentaires uniques;Canadian Journal of Electrical and Computer Engineering;2018

3. Toward a Faster Screening of Faulty Digital Chips via Current-Bound Estimation Based on Device Size and Threshold Voltage;Journal of Low Power Electronics and Applications;2016-05-06

4. Bridging high performance and low power in processor design;Proceedings of the 2014 international symposium on Low power electronics and design;2014-08-11

5. Asynchronous Fine-Grain Power-Gated Logic;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-06

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