Chemical Oxide Interfacial Layer for the High-$k$-Last/Gate-Last Integration Scheme-Reference-Cited by-同舟云学术

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Chemical Oxide Interfacial Layer for the High-$k$-Last/Gate-Last Integration Scheme

Published:2012-07 Issue:7 Volume:33 Page:946-948
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Chen Ying-Tsung,Fu Ssu-I,Chiang Wen-Tai,Lin Chien-Ting,Tsai Shih-Hung,Wang Shao-Wei,Chang Shoou-Jinn

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/6224205/06204313.pdf?arnumber=6204313

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Structural and electronic properties of HfO ₂ films on Si through H ₂ O ₂ wet oxidation with improved thermal stability;Surface and Interface Analysis;2022-04-16

2. Electrical and physical characteristics of high-k gated MOSFETs with in-situ H2O and O2 plasma formed interfacial layer;Microelectronic Engineering;2015-11

3. Improved high-k stacks with chemical oxide interfacial layer by DPN/PNA treatment;Current Applied Physics;2015-03

4. Kink effect for 28 nm n-channel field-effect transistors after decoupled plasma nitridation treatment with annealing temperatures;International Journal of Nanotechnology;2015

5. Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process;Journal of Semiconductors;2014-10

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