A Reliable 3D MLC PCM Architecture with Resistance Drift Predictor
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6900116/6903544/06903580.pdf?arnumber=6903580
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A survey on techniques for improving Phase Change Memory (PCM) lifetime;Journal of Systems Architecture;2023-11
2. DTC: A Drift-Tolerant Coding to Improve the Performance and Energy Efficiency of -Level-Cell Phase-Change Memory;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-10
3. Simultaneously low resistance drift and ultra‐fast phase change speed based on GeSb/Sb multilayer thin films;Journal of the American Ceramic Society;2023-09-19
4. eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022
5. Seeds of SEED: R-SAW: New Side Channels Exploiting Read Asymmetry in MLC Phase Change Memories;2021 International Symposium on Secure and Private Execution Environment Design (SEED);2021-09
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