Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study-Reference-Cited by-同舟云学术

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Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study

Published:2020-09-15 Issue: Volume: Page:
ISSN:
Container-title:2020 Forum for Specification and Design Languages (FDL)
language:
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Author:

Herdt Vladimir,Grosse Daniel,Jentzsch Eyck,Drechsler Rolf

Funder

Federal Ministry of Education and Research (BMBF)

BMBF project VerSys

German Research Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9226655/9232930/09232941.pdf?arnumber=9232941

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. A Multi-Core Verification Method of Vector Instructions Based on Spike;2023 Asia-Pacific Conference on Image Processing, Electronics and Computers (IPEC);2023-04-14

4. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing;Proceedings of the Great Lakes Symposium on VLSI 2022;2022-06-06

5. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging;2022 Design, Automation & Test in Europe Conference & Exhibition (DATE);2022-03-14

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