Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing-Reference-Cited by-同舟云学术

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

Published:2022-06-06 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Great Lakes Symposium on VLSI 2022
language:
Short-container-title:

Author:

Bruns Niklas¹,Herdt Vladimir²,Große Daniel³,Drechsler Rolf²

Affiliation:

1. University of Bremen, Bremen, Germany

2. University of Bremen & DFKI GmbH, Bremen, Germany

3. Johannes Kepler University & DFKI GmbH, Linz, Austria

Funder

BMBF

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3526241.3530340

Reference39 articles.

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2. 2013. RISC-V ISA Tests. https://github.com/riscv/riscv-tests. 2013. RISC-V ISA Tests. https://github.com/riscv/riscv-tests.

3. 2016. Fuzz testing in Chromium. https://chromium.googlesource.com/chromium/src/+/master/testing/libfuzzer/README.md 2016. Fuzz testing in Chromium. https://chromium.googlesource.com/chromium/src/+/master/testing/libfuzzer/README.md

4. 2016. SpinalHDL. https://github.com/SpinalHDL/SpinalHDL 2016. SpinalHDL. https://github.com/SpinalHDL/SpinalHDL

5. 2018. AFL: Understanding the status screen. https://github.com/google/AFL/blob/fab1ca5ed7e3552833a18fc2116d33a9241699bc/docs/status_screen.txt. 2018. AFL: Understanding the status screen. https://github.com/google/AFL/blob/fab1ca5ed7e3552833a18fc2116d33a9241699bc/docs/status_screen.txt.

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1. Introduction;Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes;2024

2. Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation;Chips;2023-09-08