Evaluating the Impact of Aging on Path-Delay Self-Test Libraries-Reference-Cited by-同舟云学术

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Evaluating the Impact of Aging on Path-Delay Self-Test Libraries

Published:2023-10-03 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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Author:

Cantoro Riccardo¹,Sartoni Sandro¹,Reorda Matteo Sonza¹,Anghel Lorena²,Portolan Michele²

Affiliation:

1. Politecnico di Torino

2. Univ Grenoble Alpes,CNRS, Grenoble INP, TIMA,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10313343/10313345/10313531.pdf?arnumber=10313531

Reference30 articles.

1. Test program synthesis for path delay faults in microprocessor cores;lai;IEEE Intl Test Conference,2000

2. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

3. Self-Test Library Generation for In-Field Test of Path Delay Faults

4. Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor

5. Mibench-embedded benchmark;bennett,2023

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