A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions-Reference-Cited by-同舟云学术

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A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions

Published:2008-04 Issue: Volume: Page:
ISSN:1093-0167
Container-title:26th IEEE VLSI Test Symposium (vts 2008)
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Author:

Christou K.,Michael M.K.,Bernardi P.,Grosso M.,Sanchez E.,Reorda M. Sonza

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4511672/4511673/04511756.pdf?arnumber=4511756

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test;2024 IEEE European Test Symposium (ETS);2024-05-20

2. Self-Test Library Generation for In-Field Test of Path Delay Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

3. Evaluating the Impact of Aging on Path-Delay Self-Test Libraries;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

4. A guided debugger-based fault injection methodology for assessing functional test programs;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

5. On the integration and hardening of Software Test Libraries in Real-Time Operating Systems;2023 IEEE 24th Latin American Test Symposium (LATS);2023-03-21

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