Comparative Analysis of Parallel and Cascaded Architectures for the Realization of High-Speed FIR Filters with FPGA-Reference-Cited by-同舟云学术

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Comparative Analysis of Parallel and Cascaded Architectures for the Realization of High-Speed FIR Filters with FPGA

Published:2023-08-03 Issue: Volume: Page:
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Container-title:2023 5th International Conference on Inventive Research in Computing Applications (ICIRCA)
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Author:

Kumari Apurva¹,Mahidhar Lolla¹,Manideep Kotha¹,Mounika Kodali¹

Affiliation:

1. B V Raju Institute of Technology,Dept. of ECE,Narsapur,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10220576/10220579/10220881.pdf?arnumber=10220881

Reference28 articles.

1. FPGA-based digital Filter Design for Biomedical Signal

2. Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter

3. FPGA Implementation of Higher Order FIR Filter

4. Implementation and designing of FIR filters using kaiser window for de-noising of electrocardiogram signals on FPGA

5. An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Hybrid Approach to Optimized n-bit Multiplier Design on FPGA Leveraging Recursive-Wallace Tree with AI Centric Enhancements for FIR Filters and Neural Network Inference;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

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