Implementation and designing of FIR filters using kaiser window for de-noising of electrocardiogram signals on FPGA-Reference-Cited by-同舟云学术

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Implementation and designing of FIR filters using kaiser window for de-noising of electrocardiogram signals on FPGA

Published:2016-11 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE 7th Power India International Conference (PIICON)
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Author:

Kumar Surender,Mehra Rajesh,Chandni

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8055167/8077148/08077428.pdf?arnumber=8077428

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Analysis of Parallel and Cascaded Architectures for the Realization of High-Speed FIR Filters with FPGA;2023 5th International Conference on Inventive Research in Computing Applications (ICIRCA);2023-08-03

2. A New Algorithm (ESA-DE) for Designing FIR Digital Filters;Wireless and Satellite Systems;2019

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