Characterization and Modeling of I-V, C-V and Trapping behavior of SiC Power MOSFETs
Author:
Affiliation:
1. Indian Institute of Technology Kanpur,Department of Electrical Engineering,Kanpur,India,208016
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10102944.pdf?arnumber=10102944
Reference8 articles.
1. BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect
2. Robust compact model of high voltage mosfet's drift region;pahwa;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2022
3. BSIM6: Analog and RF Compact Model for Bulk MOSFET
4. Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model
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1. Trapping/Detrapping Kinetic Modeling Under Positive/Negative Gate Stress Including Inhibition Dynamics in 4H-SiC MOS Capacitors;IEEE Transactions on Electron Devices;2024-01
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