Trapping/Detrapping Kinetic Modeling Under Positive/Negative Gate Stress Including Inhibition Dynamics in 4H-SiC MOS Capacitors
Author:
Affiliation:
1. International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India
Funder
“Center for Advanced Semiconductor Technology Research” from the Featured Areas Research Center Program within the framework of the Higher Education Sprout Project
Ministry of Education (MOE) in Taiwan
National Science and Technology Council (NSTC), Taiwan
UMC Fellowship during his Ph.D. research
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10382412/10319448.pdf?arnumber=10319448
Reference32 articles.
1. Material science and device physics in SiC technology for high-voltage power devices
2. 1.2 kV 4H-SiC VDMOSFETs with Si-implanted Surface: Performance Enhancement and Reliability Evaluation
3. 1100 V, 22.9 mΩcm2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation
4. Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability
5. BSIM6: Analog and RF Compact Model for Bulk MOSFET
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